Non-volatile memory devices, such as electrically programmable and UV erasable read only memories (EPROMs) and electrically erasable and programmable read only memories (EEPROMs), comprise core arrays of memory cells, with each cell including a variable threshold transistor. Such transistors are programmable by shifting the voltage threshold for conduction.
FIG. 1 shows a portion of a memory array 10 according to the prior art, including memory cells 11, each memory cell in turn including a pair of transistors, the first one being a select transistor 11a and the second being a variable threshold transistor 11b. According to one version of the prior art, the select transistors 11a are n-channel enhancement transistors, and the variable threshold transistors 11b are n-channel native transistors. Other kinds of memory cells 11 including a greater number of transistors are known in the prior art as well.
The memory cells 11 shown in FIG. 1 are interconnected by bit lines 12, sense lines 13, and word lines 19, as shown. In particular, the drains of the n-channel enhancement select transistors 11a will be connected to an adjacent bit line 12. The gates of select transistors 11a and variable threshold transistors 11b will respectively be connected to adjacent word lines 19 and sense lines 13.
FIG. 2 shows a non-volatile memory arrangement 20 of the prior art, including a selected portion of memory array 10 from FIG. 1. Again, memory cell 11 is shown including a pair of transistors respectively select transistor 11a and variable threshold transistor 11b. As before, according to an n-channel implementation of select and variable threshold transistors, 11a and 11b, the drain of select transistor 11a will be connected to bit line 12, and the respective gates of select and variable threshold transistors, 11a and 11b, will be connected respectively to word and sense lines, 19 and 13. Word line 19 is driven by a word line decoder 22 which is subject to control signals, PWRUP, which it has been programmed to recognize.
Additionally shown in prior art FIG. 2 is read select transistor 24 which is connected to read select line 26. When read operation is active, read select transistor 24 is turned on, electrically connecting bit line 12 to a data bus 27 which is connected to a sense amplifier 29. Bit line 12 is further connected to a bit latch 30 through a programming select transistor 32 which is controlled at its gate by a programming select line 34. According to a typical arrangement of the prior art, read select transistor 24 is an n-channel enhancement transistor, and programming select transistor 32 is an n-channel enhancement transistor.
Word line 19 of FIG. 2 according to the prior art is connected to a word line latch 42 which is provided with a word line bias voltage, VWL, from word line voltage source 44. Word line latch 42 includes word line latch transistors 46 and 48. Word line latch transistors 46 and 48 are connected at their sources to the positive voltage side of word line voltage source 44. The respective gates of word line latch transistors 46 and 48 are connected to each other's drains. In other words, the gate of word line latch transistor 46 is connected to the drain of word line latch transistor 48, and the gate of word line latch transistor 46 is connected to the drain of word line latch transistor 48. Word line latch 42 additionally includes an n-channel enhancement word line latch transistor 50 which is connected at its gate to word line 19 and to the drain of word line latch transistor 46. The drain of word line latch transistor 50 is connected to the gate of word line latch transistor 46 and to the drain of word line latch transistor 48.
Sense line 13 in prior art FIG. 2 is further connected to first and second reference pass transistors 35 and 40, both of them being n-channel enhancement devices, at their respective sources. The respective drains of first and second reference pass transistors 35 and 40 are connected to the respective positive sides of first and second reference voltage sources, 36 and 38. The gates of respective first and second reference pass transistors 35 and 40, are connected respectively to word line 19 and to the output of word line latch 42.
According to the prior art, when the circuitry of FIG. 2 is subject to read operation, the conductive state of memory cell 11 is queried by connecting bit line 12 to sense amplifier 29 and by applying appropriate bias voltages to the selected bit, sense, and word lines 12, 13, and 19. If cell select transistor 11a is turned on and the bias voltage applied to the sense line 13 exceeds the threshold of the variable threshold transistor 11b, then current will flow from bit line 12 to ground through cell 11, and sense amplifier 29 will detect a "low" state, which is so defined according to convention. Conversely, if the bias voltage applied to sense line 13 does not exceed the threshold of variable threshold transistor 11b, then no current will flow through cell 11, and sense amplifier 29 will detect a "high" state.
Thus, the low or high state of a particular cell 11 corresponds to the low or high threshold of variable threshold transistor 11b. Irrespective of the conductive state of selected memory cell 11 during a read operation, particular bias voltages will be applied to its respective terminals, i.e., bit line 12, sense line 13, and word line 19. While these bias voltages will have had the desired effect of providing the necessary stimulus for detecting the conductive state of memory cell 11, the bias voltages also may have had the undesirable effect of disturbing the programmed state of variable threshold transistor 11b. This deleterious effect of the various bias voltages is unfortunately enhanced by time, i.e., the longer the particular voltage biases are applied, the more likely it is that the programmed threshold of transistor 11b will have been disturbed. Thus, the bias voltages applied to memory cell 11 act as undesired stress voltages.
During programming operation, the bias voltages applied to the various terminals of memory cell 11 are much higher than those applied during read operation. Again, while these high bias voltages have the desired effect of modifying the threshold of the programmable memory cell 11, they also have the undesired effect of stressing the various transistors in memory cell 11, which causes a negative impact on long term reliability.
Accordingly, an object of the invention is to reduce stress during read and programming operations of the memory cells in semiconductor memory arrays by minimizing the amount of time that the various bias voltages are applied to the memory cells.
A further object of the invention is to increase the effective operable lifetime and reliability of the core memory in non-volatile semiconductor memory arrays.